FIG. 1 shows one example of a resistor-based memory array architecture called a crosspoint array. The memory array 8 includes a plurality of row lines 6 arranged orthogonally to a plurality of column lines 12. Each row line is coupled to each of the column lines by a respective resistive memory cell 14. The resistance value of each memory cell stores one of two or more logical values depending on which of a plurality of resistance values it is programmed to exhibit. A characteristic of the crosspoint array having resistance cells 14 connected to row and column lines is that there are no memory cell access transistors in the array.
A MRAM device is one approach to implementing a resistance-based memory. In a MRAM each resistive memory cell typically includes a pinned magnetic layer, a sensed magnetic layer and a tunnel barrier layer between the pinned and sensed layers. The pinned layer has a fixed magnetic alignment, and a magnetic alignment of the sensed layer can be programmed to different orientations. The resistance of the cell varies, depending on the alignment of the sensed layer. One resistance value, e.g., a higher value, is used to signify a logic “one” while another resistance value, e.g., a lower value, is used to signify a logic “zero”. The stored data is read by sensing respective resistance values of memory cells and interpreting the resistance values thus sensed as logic states of the stored data.
For binary logic state sensing, the absolute magnitude of memory cell resistance need not be known, only whether the resistance is above or below a threshold value that is intermediate to the logic one and logic zero resistance values. Nonetheless, sensing the logic state of a MRAM memory element is difficult because the technology of the MRAM device impose multiple constraints.
A MRAM cell resistance is sensed at the column line of the addressed cell. In order to sense the cell, a row line connected to that cell is typically grounded while the remaining row lines and column lines are held at a particular voltage. Reducing or eliminating transistors from a memory cell tends to reduce the cell area requirements, increasing storage density and reducing costs. A cell of a crosspoint array, as discussed above, includes no transistors. This is achieved by allowing each resistive element to remain electrically coupled to respective row and column lines at all times. As a result, when a memory cell is sensed, it is also shunted by a significant sneak current path through the other memory cells of the addressed row line.
In a conventional MRAM device, the high resistance state has a resistance of about 1MΩ. An element in a low resistance state has a resistance of about 950 KΩ. The differential resistance between a logic one and a logic zero is, thus, typically about 50KΩ or about 5% of scale. Accordingly, a sensing voltage across a sensed MRAM device varies by about 5% of scale between the logic one and logic zero states.
One approach to sensing MRAM resistance is to integrate a current corresponding to sensing voltage over time, and to sample the resulting integrand voltage. This can be done by applying a voltage to an input of a transductance amplifier, and accumulating a current output by the amplifier with a capacitor.
FIG. 2 shows the theoretical change of voltage on such a capacitor with time. The time interval tm that the capacitor voltage Vcap takes to rise from an initial voltage Vinit to a reference voltage Vref is related to the voltage applied at the input of the transductance amplifier.
A conventional sensing technique compares Vcap with Vref, allowing Vcap to increase until Vcap exceeds Vref and then discharging a capacitor until Vcap is again below Vref. Pulses indicating a comparison result can be counted to measure the sensing voltage, which, in turn, indicates an element's resistance state. Problems arise, however, when large counts accumulate during a sampling period.